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synchronous current - mod e with constant on - time, pwm buck controller data sheet adp1872 / ADP1873 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its u se. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2012 analog devices, inc. all rights reserved. features power input voltage as low as 2.75 v to 20 v bias supply voltage range: 2.75 v to 5.5 v minimum output voltage : 0.6 v 0.6 v reference voltage with 1.0% a ccuracy suppo rts all n - channel mosfet power s tage s available in 300 k hz, 600 khz , and 1.0 mhz options no current - sense resistor required power saving mode (psm) for light loads (ADP1873 only) resistor - programmable current - sense gain thermal overload protection s hort - circuit protection precision enable input integrated boot strap diode for high - side drive 1 40 a shutdown supply current starts into a pre charged load small, 10 - lead msop package applications telecom and networking systems mid to high end servers set - top boxes dsp core power supplies typical applications circuit + comp/en bst fb drvh gnd sw vdd drvl pgnd vin c c c vdd c vdd2 c c2 r c r top r bot v out v dd = 2.75v to 5.5v q1 q2 r res l c out v out c bst load 5a c in v in = 2.75v to 20v adp1872/ ADP1873 08297-001 figure 1. 100 95 90 85 80 75 70 65 60 55 50 45 100 1k 10k 100k efficiency (%) load current (ma) v dd = 5.5v, v in = 5.5v (psm) v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 13.0v (psm) v dd = 5.5v, v in = 5.5v t a = 25c v out = 1.8v f sw = 300khz wurth inductor: 744325120, l = 1.2h, dcr = 1.8m infineon fets: bsc042n03ms g (upper/lower) 08297-002 figure 2 . adp1872 efficiency vs. load current (v out = 1.8 v, 300 khz) general description the adp1872/ADP1873 are versatile current - mode, synchronous step - down controllers that provide superior transient response , optimal stability, and current limit protection by using a constant on - time, pseudo - fixed frequency with a programmable current - sense gain, current - control scheme. in addition, these devices offer optimum performance at low duty cycles by u s ing valley cu rrent - mode control architecture. this allows the adp1872/ADP1873 to drive all n - channel power stages to regulate output voltages as low as 0.6 v. t he ADP1873 is the power saving mode (psm) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the power saving mode ( psm ) version (ADP1873) section for more information). available in three frequency options (300 khz, 600 khz, and 1.0 mhz, plus the psm option), the adp1872/ADP1873 are well suited for a wide range of applications. these ics not only operate from a 2.75 v to 5.5 v bias supply , but can also accept a power input as high as 20 v. in addition, an internally fix ed, s oft start period is included to limit input in - rush current from the input supply during startup and to provide reverse current protection during soft start for a pre - charged output. the low - side current - sense, current - gain scheme and integration of a boos t diode , along with the psm/forced pulse - width modulation (pwm) option, reduce the external part count and improve efficiency. the adp1872/ADP1873 operate over the ? 40c to +125c junction temperature range and are available in a 10 - lead msop.
adp1872/ADP1873 data sheet rev. b | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 boundary condition .................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 adp1872/ADP1873 block digram .............................................. 17 theory of operation ...................................................................... 18 startup .......................................................................................... 18 soft start ...................................................................................... 18 precision enable circuitry ........................................................ 18 undervoltage lockout ............................................................... 18 thermal shutdown ..................................................................... 18 programming resistor (res) detect circuit .......................... 19 valley current-limit setting .................................................... 19 hiccup mode during short circuit ......................................... 20 synchronous rectifier ................................................................ 21 power saving mode (psm) version (ADP1873) .................... 21 timer operation ........................................................................ 21 pseudo-fixed frequency ........................................................... 22 applications information .............................................................. 23 feedback resistor divider ........................................................ 23 inductor selection ...................................................................... 23 output ripple voltage (v rr ) .................................................. 23 output capacitor selection ....................................................... 23 compensation network ............................................................ 24 efficiency consideration ........................................................... 25 input capacitor selection .......................................................... 26 thermal considerations ............................................................ 27 design example .......................................................................... 27 external component recommendations .................................... 30 layout considerations ................................................................... 32 ic section (left side of evaluation board) ............................. 37 power section ............................................................................. 37 differential sensing .................................................................... 37 typical application circuits ......................................................... 38 dual-input, 300 khz high current application circuit ...... 38 single-input, 600 khz application circuit ............................. 38 dual-input, 300 khz high current application circuit ...... 39 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 7/12rev. a to rev. b changed r on = 15 m/100 k valley current level value from 7.5 to 3.87; table 6 .......................................................................... 20 changes to ordering guide .......................................................... 40 3/10rev. 0 to rev. a changes to figure 1 .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to figure 59 caption and figure 60 caption .............. 16 changes to figure 64 ...................................................................... 17 changes to timer operation section .......................................... 22 changes to table 7 .......................................................................... 23 changes to inductor section ......................................................... 28 changes to table 9 .......................................................................... 31 changes to figure 82 ...................................................................... 32 changes to figure 83 ...................................................................... 33 changes to figure 84 ...................................................................... 34 changes to figure 85 ...................................................................... 35 changes to figure 86 ...................................................................... 36 changes to differential sensing section and figure 88 ............ 37 changes to figure 89 and figure 90............................................. 38 changes to figure 91 ...................................................................... 39 updated outline dimensions ....................................................... 40 10/09revision 0: initial version
data sheet adp1872/ADP1873 rev. b | page 3 of 40 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality cont rol (sqc). vdd = 5 v, bst ? sw = 5 v , vin = 13 v . the specifications are valid for t j = ? 40c to +12 5c, unless otherwise specified. table 1 . parameter symbol conditions min typ max unit power supply characteristics high i nput voltage range vin adp1872armz - 0.3 /ADP1873armz - 0.3 (300 khz) 2.7 5 12 20 v adp1872armz - 0.6 /ADP1873armz - 0.6 (600 khz) 2.7 5 12 20 v adp1872armz - 1.0 /ADP1873armz - 1.0 (1.0 mhz) 3.0 12 20 v low input voltage range vdd c in = 1 f to pgnd, c in = 0.22 f to gnd adp1872armz - 0.3/ADP1873armz - 0.3 (300 khz) 2.7 5 5 5.5 v adp1872armz - 0.6/ADP1873armz - 0.6 (600 khz) 2.7 5 5 5.5 v adp1872armz - 1.0/ADP1873armz - 1.0 (1.0 mhz) 3.0 5 5.5 v quiescent current i q_dd + i q_bst fb = 1.5 v, no switching 1.1 ma shu tdown current i dd, sd + i bst, sd comp/en < 2 85 mv 140 215 a undervoltage lockout uvlo rising vdd (see figure 34 for temperature variation) 2.65 v uvlo hysteresis falling vdd from operational state 190 mv soft start soft start period see figure 57 3.0 ms error amplifer fb regulation voltage v fb t j = 25c 600 mv t j = ?40c to +85c 595 .5 600 605. 4 mv t j = ?40c to +125c 59 4.2 600 606.5 mv transconductance g m 300 5 15 7 3 0 s fb input leakage current i fb, l eak fb = 0.6 v, comp/en = released 1 50 na current - sense amplifier gain programming resistor (res) value from drvl to pgnd res = 47 k 1 % 2 . 7 3 3. 3 v/v res = 22 k 1 % 5. 5 6 6. 5 v/v res = none 11 12 13 v/v res = 100 k 1 % 22 24 26 v/v switching frequency typical values m easured at 50% time points with 0 nf at drvh and drvl ; maximum values are guaranteed by bench evaluation 1 adp1872armz - 0.3/ ADP1873armz - 0.3 (300 khz) 300 khz on - time vin = 5 v, v out = 2 v, t j = 25c 1120 1200 1280 ns minimum on - time vin = 20 v 145 190 ns minimum off - time 84% duty cycle (maximum) 320 3 85 ns adp1872armz - 0.6/ ADP1873armz - 0.6 (600 khz) 600 khz on - time vin = 5 v, v out = 2 v, t j = 25c 500 520 5 80 ns minimum on - time vin = 20 v, v out = 0.8 v 82 110 ns minimum off - time 65% duty cycle (maximum) 3 20 385 ns adp1872armz - 1.0/ ADP1873a rmz - 1.0 (1.0 mhz) 1.0 mhz on - time vin = 5 v, v out = 2 v, t j = 25c 2 85 312 3 40 ns minimum on - time vin = 20 v 6 0 85 ns minimum off - time 45% duty cycle (maximum) 320 385 ns
adp1872/ADP1873 data sheet rev. b | page 4 of 40 parameter symbol conditions min typ max unit output driver characteristics high - side driver output sour ce resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 2 3 .5 output sink resistance i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.8 2 rise time 2 t r, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 59 ) 25 ns fall time 2 t f, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 60) 11 ns low - side driver output source resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 1.7 3 output sink resistance i si nk = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.75 2 rise time 2 t r, drvl vdd = 5.0 v, c in = 4.3 nf (see figure 60) 18 ns fall time 2 t f, drvl vdd = 5.0 v, c in = 4.3 nf (see figure 59) 16 ns propagation delays drvl fall to drvh rise 2 t tpdh , drvh bst ? sw = 4.4 v ( see figure 59) 22 ns drvh fall to drvl rise 2 t tpdh , drvl bst ? sw = 4.4 v (see figure 60) 2 4 ns sw leakage current i sw , leak bst = 25 v, sw = 20 v , vdd = 5.5 v 110 a integrated rectifier channel impedance i sink = 10 ma 22 precision enable threshold logic high level vin = 2.9 v to 20 v, vdd = 2.75 v to 5.5 v 235 285 330 mv enable hysteresis vi n = 2.9 v to 20 v, vdd = 2.75 v to 5.5 v 35 mv comp voltage comp clamp low voltage v comp ( low ) from disable state, release comp/en pin to enable device ( 2.75 v vdd 5.5 v) 0.47 v comp clamp high voltage v comp ( high ) ( 2.75 v vdd 5.5 v) 2.55 v comp zero current threshold v comp_zct ( 2.75 v vdd 5.5 v) 1.15 v thermal shutdown t tmsd thermal shutdown threshold rising temperature 155 c thermal shutdown hysteresis 15 c hiccup current limit timing 6 ms 1 the maximum specified value s are with the closed loop measured at 10% to 90% time points (see figure 59 and figure 60 ), c gat e = 4.3 nf and upper - and lower - side mosfets being infineon bsc042n03ms g. 2 not automatic test equipment (ate) tested.
data sheet adp1872/ADP1873 rev. b | page 5 of 40 a bsolute m aximum ratings table 2 . parameter rating vdd to gnd ?0.3 v to +6 v vin to p gnd ?0.3 v to +28 v fb, comp/en to gnd ?0.3 v to (vdd + 0.3 v) drvl to pgnd ?0.3 v to (vdd + 0.3 v) sw to pgnd ? 0 .3 v to +28 v sw to pgnd ? 2 v p ulse (20 ns) bst to sw ?0.6 v to (vdd + 0.3 v) bst to pgnd ?0.3 v to + 28 v drvh to sw ?0.3 v to vdd pgnd to gnd 0.3 v operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j - std -020 ma ximum soldering lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above t hose indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified , all other voltages are referenced to p gnd. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit ja (10 - lead msop) 2 - layer board 213.1 c/w 4 - layer board 171.7 c/w boundary condition in determin ing the values given in table 2 and table 3 , natural convection was used to transfer heat to a 4 - layer evaluation board. esd caution
adp1872/ADP1873 data sheet rev. b | page 6 of 40 pin configuration and fu nction descriptions vin 1 comp/en 2 fb 3 gnd 4 vdd 5 bst 10 sw 9 drvh 8 pgnd 7 drvl 6 adp1872 top view (not to scale) 08297-003 figure 3. pin configuration table 4 . pin function descript ions pin o. mnemonic description 1 vin high input voltage. connect vin to the drain of the upper - side mosfet. 2 comp/en output of the internal error amplifier/ic enable. when this pin functions as en, a pplying 0 v to this pin disables the ic. 3 fb noni nverting input of the internal error amplifier. this is the node where the feedback resistor is connected. 4 gnd analog ground reference pin of the ic. all sensitive analog components should be connected to this ground pla ne (see the layout considerations section). 5 vdd bias voltage su pply for the adp1872 /ADP1873 controller ( i nclud es the output gate drivers ) . a bypass capacitor of 1 f directly from this pin to pgnd and a 0.1 f across vdd and gnd are recommende d. 6 drvl drive output for the external l ower side , n - channel mosfet. this pin a lso serves as the current - sense gain setting pin (see figure 68). 7 pgnd power gnd. ground for the lower side gate driver and lower side, n - channel mosfet . 8 drvh drive output for the external upper side , n - channel mosfet. 9 sw switch node connection. 10 bst boots trap for the upper side mosfet gate drive circuitry. an internal boot rectifier (diode) is connected between vdd and bst . a capacitor from bst to sw is required. an external schottky diode can also be connected between vdd and bst for increased gate drive capability.
data sheet adp1872/ADP1873 rev. b | page 7 of 40 typical performance characteristics 100 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744355147, l = 0.47h, dcr: 0.80m ? infineon fets: bsc042n03ms g (u pper/lower) t a = 25c v dd = 5.5v, v in = 13v (psm) v dd = 5.5v, v in = 5.5v v dd = 3.6v, v in = 5.5v v dd = 5.5v, v in = 13v v dd = 3.6v, v in = 13v v dd = 5.5v, v in = 16.5v v dd = 3.6v, v in = 16.5v v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 5.5v (psm) 08297-004 figure 4. efficiency300 khz, v out = 0.8 v 100 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744325120, l = 1.2h, dcr: 1.8m ? infineon fets: bsc042n03ms g (upper/lower) t a = 25c v dd = 5.5v, v in = 5.5v (psm) v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 5.5v v dd = 5.5v, v in = 16.5v v dd = 5.5v, v in = 13v (psm) v dd = 3.6v, v in = 3.6v v dd = 5.5v, v in = 13v v dd = 3.6v, v in = 5.5v 08297-005 figure 5. efficiency300 khz, v out = 1.8 v 100 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 7443551200, l = 2h, dcr: 2.6m ? infineon fets: bsc042n03ms g (u pper/lower) t a = 25c 13v in 16.5v in v dd = 2.7v 13v in 16.5v in v dd = 3.6v 13v in 16.5v in v dd = 5.5v v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 16v (psm) 08297-006 figure 6. efficiency300 khz, v out = 7 v 100 15 25 35 20 30 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744355147, l = 0.47h, dcr: 0.80m ? infineon fets: bsc042n03ms g (upper/lower) t a = 25c v dd = 5.5v, v in = 13v (psm) v dd = 5.5v, v in = 5.5v (psm) v dd = 5.5v, v in = 5.5v v dd = 3.6v, v in = 5.5v v dd = 5.5v, v in = 13v v dd = 5.5v, v in = 16.5v v dd = 5.5v, v in = 16.5v (psm) 08297-007 figure 7. efficiency600 khz, v out = 0.8 v 100 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744325120, l = 1.2h, dcr: 1.8m ? infineon fets: bsc042n03ms g (upper/lower) t a = 25c v dd = 5.5v , = v in = 5.5(psm) v dd = 5.5v, v in = 5.5v v dd = 5.5v, v in = 16.5v v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 13v (psm) v dd = 3.6v, v in = 5.5v v dd = 5.5v, v in = 13v 08297-008 figure 8. efficiency600 khz, v out = 1.8 v 100 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 7443551200, l = 2h, dcr: 2.6m ? infineon fets: bsc042n03ms g (upper/lower) t a = 25c v dd = 5.5v, v in = 13v (psm) v dd = 3.6v,v in = 13v v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 13v v dd = 3.6v, v in = 16.5v v dd = 5.5v, v in = 16.5v 08297-009 figure 9. efficiency600 khz, v out = 5 v
adp1872/ADP1873 data sheet rev. b | page 8 of 40 100 20 30 25 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744303012, l = 0.12h, dcr: 0.33m ? infineon fets: bsc042n03ms g (u pper/lower) t a = 25c v dd = 5.5v, v in = 5.5v v dd = 5.5v, v in = 5.5v (psm) v dd = 5.5v, v in = 16.5v v dd = 3.6v, v in = 5.5v v dd = 3.6v, v in = 3.6v v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 13v (psm) v dd = 5.5v, v in = 13v 08297-010 figure 10. efficiency1.0 mhz, v out = 0.8 v 100 20 30 25 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100k 10k 1k efficiency (%) load current (ma) wurth ind: 744303022, l = 0.22h, dcr: 0.33m ? infineon fets: bsc042n03ms g (u pper/lower) t a = 25c v dd = 5.5v, v in = 16.5v (psm) v dd = 5.5v, v in = 5v (psm) v dd = 5.5v, v in = 16.5v v dd = 3.6v, v in = 13v v dd = 3.6v, v in = 16.5v v dd = 5.5v, v in = 13v (psm) v dd = 5.5v, v in = 13v v dd = 5.5v, v in = 5v 08297-011 figure 11. efficiency1.0 mhz, v out = 1.8 v 100 20 30 25 35 40 45 50 55 60 65 70 75 80 85 90 95 100 10k 1k efficiency (%) load current (ma) wurth ind: 744325072, l = 0.72h, dcr: 1.65m ? infineon fets: bsc042n03ms g (u pper/lower) t a = 25c v dd = 5.5v, v in = 5v (psm) v dd = 5.5v, v in = 16.5v (psm) v dd = 5v, v in = 16.5v v dd = 5v, v in = 13v 08297-012 figure 12. efficiency1.0 mhz, v out = 4 v 0.8030 0.8025 0.8020 0.8015 0.8010 0.8005 0.8000 0.7995 0.7990 0.7985 0.7980 0.7975 0.7970 0.7965 0.7960 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-013 figure 13. output voltage accuracy300 khz, v out = 0.8 v 1.821 1.816 1.811 1.806 1.801 1.796 1.791 1.786 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-014 figure 14. output voltage accuracy300 khz, v out = 1.8 v 7.000 6.955 6.960 6.965 6.970 6.975 6.980 6.985 6.990 6.995 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v dd = 3.6v, v in = 13v v dd = 3.6v, v in = 16.5v v dd = 5.5v, v in = 13v v dd = 5.5v, v in = 16.5v 08297-015 figure 15. output voltage accuracy300 khz, v out = 7 v
data sheet adp1872/ADP1873 rev. b | page 9 of 40 1.801 1.789 1.790 1.791 1.792 1.793 1.794 1.795 1.796 1.797 1.798 1.799 1.800 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-016 figure 16. output voltage accuracy600 khz, v out = 1.8 v 5.044 5.042 5.040 5.038 5.036 5.034 5.032 5.030 5.028 5.026 5.024 5.022 5.020 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v dd = 5.5v, v in = 13v v dd = 5.5v, v in = 16.5v 08297-017 figure 17. output voltage accuracy600 khz, v out = 5 v 0.807 0.806 0.805 0.804 0.803 0.802 0.801 0.800 0.799 0.798 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-018 figure 18. output voltage accuracy1 mhz, v out = 0.8 v 1.810 1.809 1.808 1.807 1.806 1.805 1.804 1.803 1.802 1.801 1.800 1.799 1.798 1.797 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-019 figure 19. output voltage accuracy1.0 mhz, v out = 1.8 v 4.050 4.045 4.040 4.035 4.030 4.025 4.020 4.015 4.010 4.005 4.000 3.995 3.990 3.985 3.980 3.975 3.970 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08297-020 figure 20. output voltage accuracy1.0 mhz, v out = 4 v 0.6030 0.5975 0.5980 0.5985 0.5990 0.5995 0.6000 0.6005 0.6010 0.6015 0.6020 0.6025 ?40.0 ?7.5 122.5 90.0 57.5 25.0 feedback voltage (v) temperature (c) v dd = 2.7v, v in = 2.7v, 3.6v v dd = 3.6v, v in = 3.6v to 16.5v v dd = 5.5v, v in = 5.5v, 13v, 16.5v 08297-021 figure 21. feedback voltage vs. temperature
adp1872/ADP1873 data sheet rev. b | page 10 of 40 335 325 315 305 295 285 275 265 255 245 235 225 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 frequency (khz) v in (v) +125c +25c ?40c no load v dd = 5.5v v dd = 3.6v 08297-022 figure 22. switching frequency vs. high input voltage, 300 khz, 10% of 12 v 650 600 550 500 450 400 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 frequency (khz) v in (v) 08297-023 no load +125c +25c ?40c v dd = 5.5v v dd = 3.6v figure 23. switching frequency vs. high input voltage, 600 khz, v out = 1.8 v, 10% of 12 v 1000 550 600 650 700 750 800 850 900 950 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 frequency (khz) v in (v) +125c +25c ?40c v dd = 5.5v v dd = 3.6v 08297-024 no load figure 24. switching frequency vs. high input voltage, 1.0 mhz, 10% of 12 v 340 325 310 295 280 265 250 235 220 205 190 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 13v v in = 16.5v +125c +25c ?40c 08297-025 figure 25. frequency vs. load current, 300 khz, v out = 0.8 v 360 350 340 330 320 310 300 290 280 270 260 0 20,000 16,000 18,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 13v v in = 16.5v +125c +25c ?40c 08297-026 figure 26. frequency vs. load current, 300 khz, v out = 1.8 v 358 290 294 298 302 306 310 314 318 322 326 330 334 338 342 346 350 354 0 9600 6400 7200 8000 8800 5600 4800 4000 3200 2400 1600800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 08297-027 figure 27. frequency vs. load current, 300 khz, v out = 7 v
data sheet adp1872/ADP1873 rev. b | page 11 of 40 700 190 220 250 280 310 340 370 400 430 460 490 520 550 580 610 640 670 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 16.5v v in = 13v +125c +25c ?40c 08297-028 figure 28. frequency vs. load current, 600 khz, v out = 0.8 v 815 495 515 535 555 575 595 615 635 655 675 695 715 735 755 775 795 0 20,000 16,000 18,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 16.5v v in = 13v +125c +25c ?40c 08297-029 figure 29. frequency vs. load current, 600 khz, v out = 1.8 v 705 698 691 684 677 670 663 656 649 642 635 628 621 614 607 600 0 9600 8800 8000 7200 6400 5600 4800 4000 3200 2400 1600800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 08297-030 figure 30. frequency vs. load current, 600 khz, v out =5 v 1300 1125 1150 1075 1000 925 850 775 700 625 550 475 400 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 16.5v v in = 13v +125c +25c ?40c 08297-031 figure 31. frequency vs. load current, v out = 1.0 mhz, 0.8 v 550 625 700 775 850 925 1000 1075 1150 1225 1300 1375 1450 0 20,000 16,000 18,000 14,000 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 5.5v v in = 16.5v v in = 13v +125c +25c ?40c min-off time encroachment 08297-032 figure 32. frequency vs. load current, 1.0 mhz, v out = 1.8 v 1000 1450 1400 1350 1300 1250 1200 1150 1100 1050 0 8000 800 1600 2400 3200 4000 4800 5600 6400 7200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08297-033 figure 33. frequency vs. load current, 1.0 mhz, v out = 4 v
adp1872/ADP1873 data sheet rev. b | page 12 of 40 2.649 2.658 2.657 2.656 2.655 2.654 2.653 2.652 2.651 2.650 ?40 120 10080604020 0 ?20 uvlo (v) temperature (c) 08297-034 figure 34. uvlo vs. temperature 40 45 50 55 60 65 70 75 80 85 90 95 100 300 400 500 600 700 800 900 1000 maximum duty cycle (%) frequency (khz) v dd = 2.7v v dd = 5.5v v dd = 3.6v +125c +25c ?40c 08297-035 figure 35. maximum duty cycle vs. frequency 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15.6 maximum duty cycle (%) v in (v) v dd = 5.5v v dd = 3.6v +125c +25c ?40c 08297-036 figure 36. maximum duty cycle vs. high voltage input (v in ) 180 680 630 580 530 480 430 380 330 280 230 ?40 120 100 80 6040 20 0 ?20 minimum off-time (ns) temperature (c) v dd = 2.7v v dd = 5.5v v dd = 3.6v 08297-037 figure 37. minimum off-time vs. temperature 180 680 630 580 530 480 430 380 330 280 230 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 minimum off-time (ns) v dd (v) +125c +25c ?40c 08297-038 figure 38. minimum off-time vs. v dd (low input voltage) 80 800 720 640 560 480 400 320 240 160 300 400 500 600 700 800 900 1000 rectifier drop (mv) frequency (khz) v dd = 2.7v v dd = 5.5v v dd = 3.6v +125c +25c ?40c 08297-039 figure 39. internal rectifier drop vs. frequency
data sheet adp1872/ADP1873 rev. b | page 13 of 40 80 1280 720 640 560 480 1040 1120 1200 960 880 800 400 320 240 160 2.73.13.53.94.34.75.15.5 rectifier drop (mv) v dd (v) v in = 5.5v v in = 16.5v v in = 13v 1mhz 300khz 08297-040 t a = 25c figure 40. internal boost rectifier drop vs. v dd (low input voltage) over vin variation 80 720 640 560 480 400 320 240 160 2.73.13.53.94.34.75.15.5 rectifier drop (mv) v dd (v) 1mhz 300khz +125c +25c ?40c 08297-041 figure 41. internal boost rectifier drop vs. v dd 8 80 64 72 56 48 40 32 24 16 2.73.13.53.94.34.75.15.5 body diode conduction time (ns) v dd (v) 1mhz 300khz +125c +25c ?40c 08297-042 figure 42. lower side mosfet body conduction time vs. v dd (low input voltage) ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m400ns a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08297-043 figure 43. power saving mode (psm) operational waveform, 100 ma ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m4.0s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08297-044 figure 44. psm waveform at light load, 500 ma ch1 5a ? ch3 10v ch4 100mv b w m400ns a ch3 2.20v t 30.6% 1 3 4 output voltage inductor current sw node 08297-045 figure 45. ccm operation at heavy load, 18 a (see figure 91 for application circuit)
adp1872/ADP1873 data sheet rev. b | page 14 of 40 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m2ms a ch1 3.40a t 75.6% 1 2 3 4 output voltage 20a step sw node low side 08297-046 figure 46 . load transient step psm enabled , 20 a (see figure 91 application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 30.6% 1 2 3 4 output voltage 20a positive step sw node low side 08297-047 figure 47. positive step during heavy load transient behavior psm enabled , 20 a, v out = 1.8 v (see figure 91 application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 48.2% 1 2 3 4 output voltage 20a negative step sw node low side 08297-048 figure 48 . negative step during heavy load transient behavior psm enabled , 20 a (see figure 91 applicatio n circuit ) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m2ms a ch1 6.20a t 15.6% 1 2 3 4 output voltage 20a step sw node low side 08297-049 figure 49 . load transient step forced pwm at light load , 20 a (see figure 91 application circuit ) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m20s a ch1 6.20a t 43.8% 1 2 3 4 output voltage 20a positive step sw node low side 08297-050 figure 50 . positive step during heavy load tran sient behavior forced pwm at light load , 20 a, v out = 1.8 v (see figure 91 application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m10s a ch1 5.60a t 23.8% 1 2 3 4 output voltage 20a negative step sw node low side 08297-051 figure 51. negative step during heavy load transient behavior forced pwm at light load , 2 0 a (see figure 91 application circuit )
data sheet adp1872/ADP1873 rev. b | page 15 of 40 ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 920mv t 49.4% 1 2 3 4 output voltage inductor current sw node low side 08297-052 figure 52 . output short - circuit behavior leading to hiccup mode ch1 5v b w ch2 10a ? ch3 10v ch4 5v m10s a ch2 8.20a t 36.2% 1 2 3 4 output voltage inductor current sw node low side 08297-053 figure 53 . magnified waveform during hiccup mode ch1 2v b w ch2 5a ? ch3 10v ch4 5v m2ms a ch1 720mv t 32.8% 1 2 3 4 output voltage inductor current sw node low side 08297-054 figure 54 . start - up behavior at heavy load, 18 a , 300 kh z (see figure 91 application circuit ) ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 720mv t 41.6% 1 2 3 4 output voltage inductor current sw node low side 08297-055 figure 55 . power - down waveform during heavy load ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m2s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08297-056 figure 56 . output voltage ripple waveform during psm operation at light load , 2 a ch1 1v b w ch2 5a ? ch3 10v b w ch4 2v m1ms a ch1 1.56v t 63.2% 1 2 3 4 output voltage inductor current sw node low side 08297-057 figure 57 . soft start and res detect waveform
adp1872/ADP1873 data sheet rev. b | page 16 of 40 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side 08297-058 t a = 25c figure 58. output driver s and sw node waveforms 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side 16ns ( t f , drvl ) 25ns ( t r , drvh ) 22ns ( t pdh , drvh ) 08297-059 t a = 25c figure 59. upper side driv er rising and lower side falling edge waveforms (c gate = 4.3 nf (upper/lower side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) 2 ch2 5v ch3 5v math 2v 20ns ch4 2v m20ns a ch2 4.20v t 39.2% 3 m 4 high side hs minus sw sw node low side 18ns ( t r , drvl ) 24ns ( t pdh , drvl ) 11ns ( t f , drvh ) 08297-060 t a = 25c figure 60. upper side driver falling an d lower side rising edge waveforms (c gate = 4.3 nf (upper/lower side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) 570 550 530 510 490 470 450 430 ?40 ?20 120 10080604020 0 transconductance (s) temperature (c) v dd = 5.5v v dd = 3.6v v dd = 2.7v 08297-061 figure 61. transconductance (g m ) vs. temperature 680 330 380 430 480 530 580 630 2.7 3.0 5.4 4.8 5.1 4.5 4.2 3.93.6 3.3 transconductance (s) v dd (v) +125c +25c ?40c 08297-062 figure 62. transconductance (g m ) vs. v dd 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 2.7 5.5 5.1 4.7 4.3 ?40c +25c +125c 3.9 3.5 3.1 quiescent current (ma) v dd (v) 08297-163 figure 63. quiescent current vs. v dd (vin = 13 v)
data sheet adp1872/ADP1873 rev. b | page 17 of 40 adp1872 /ADP1873 block digram to enable all blocks comp/en vin precision enable block t on state machine drivers v dd v dd filter pgnd bst drvh sw drvl pfm ref_zero gnd ss comp error amp ss_ref 0.6v lower comp clamp cs gain programming v reg ref_zero cs gain set cs amp pwm adc i rev comp vdd fb bias block i ss c ss 300k? 8k? 800k? adp1872/ ADP1873 08297-063 figure 64 . adp1872/ADP1873 block diagram
adp1872/ADP1873 data sheet rev. b | page 18 of 40 theory of operation the adp1872/ADP1873 are ver satile current - mode, synchronous step - down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on - time, pseudo - fixed frequency with a programmable current - sense gain, current - control sch eme. in addition, these devices offer optimum performance at low duty cycles by u s ing valley current - mode control architecture. this allows the adp1872/ ADP1873 to drive all n - channel power stages to regulate output voltages as low as 0.6 v. startup the ad p1872 /ADP1873 ha ve an input low voltage pin (v dd ) for biasing and supplying power for the integrated mosfet drivers . a bypass capacitor should be located directly across the vdd (pin 5) and pgnd (pin 7) pins . in cluded in th e power - up sequenc e is the biasin g of the current - sense amplifier , the current - sense gain circuit (see the programming resistor (res) detect circuit section ), the soft start circuit, and the error amplifier . the current - sense blocks provide valle y current information (see the programming resistor (res) detect circuit section) and are a variable of the compensation equation for loop stability (see the compensation ne twork section ). the valley current information is extracted by forcing 0.4 v across the drvl output and the pgnd pin, which generates a current depending on the resistor across drvl and pgnd in a process performed by the res detect circuit . the current th rough the resistor is used to set the current - sense amplifier gain. this process takes approximately 800 s, after which the drive signal pulses appear at the drvl and drvh pins synchronously and the output voltage begins to rise in a controlled manner thr ough the soft start sequence. the rise time of the output voltage is determined by the soft start and error amplifier blocks ( see the soft start section ). at the beginning of a soft start, the error amplifier charg e s the e xter nal compensation capacitor , causing the comp/ en pin to rise above the enable threshold of 2 85 mv , thus enabling the adp1872 /ADP1873 . soft start the adp1872/ADP1873 ha ve digital soft start circuitry , which involves a counter that initiates an i ncremental increase in cur rent , by 1 a, via a current source on every cycle through a fixed internal capacitor . the output track s th e ramping voltage by producing pwm output pulses to the upper side mosfet . the purpose is to limit the in- rush curr ent from the high voltage input supply (vin) to the output (v out ) . precision enable cir cuitry the adp1872/ADP1873 employ precision enable c irc uitr y. the enable threshold is 2 85 m v typical with 35 mv of hysteresis. the device s are enabled when the comp/en pin is r eleased , allowing the error amplifier output to rise above the enable threshold (see figure 65) . ground ing this pin disables the adp1872/ADP1873 , reducing the supply current of the device s to approximately 1 40 a. for more information, see figure 66. 0.6v 285mv ss v dd fb comp/en precision enable error amplifier to enable all blocks c c c c2 r c adp1872/ADP1873 08297-064 figure 65 . release comp/en pin to enable the adp1872/ADP1873 comp/en >2.4v 2.4v 1.0v 500mv 285mv 0v hiccup mode initialized maximum current (upper clamp) zero current usable range only after soft start period if contunuous conduction mode of operation is selected. lower clamp precision enable threshold 35mv hysteresis 08297-065 figure 66 . comp/en voltage range undervoltage lockout the unde rvoltage lockout (uvlo) feature prevents the part from operating both the upper side and low er side mosfets at extremely low or undefined input voltage (vdd) ran ges. operation at an undefined bias voltage may result in the incorrect propagation of signals to the hig h - side power switches . this , in turn , result s in invalid output behavior that can cause damage to the output devices , ultimately destroying the device tied at the output . the uvlo level has been set at 2.65 v (nominal) . thermal shutdown the ther mal shutdown is a self - protection feature to prevent the ic from da mage due to a very high operating junction temperature. if the junction temperature of the device exceed s 155 c, the part ente rs the thermal shutdown state. in this state, the device shut s off both the upper side and low er side mosfets and disable s the entire controller immediately, thus reducin g the power consumption of the ic. the part resume s operation after the junctio n temperature of the part cools to less than 140 c.
data sheet adp1872/ADP1873 rev. b | page 19 of 40 programming resistor (res) detect circuit upon startup, one of the first blocks to become active is the res detect circuit. this block powers up before soft start begins. it forces a 0.4 v reference value at the drvl output (see figure 67) and is programmed to identify four possible resistor values: 47 k, 22 k, open, and 100 k. the res detect circuit digitizes the value of the resistor at the drvl pin (pin 6). an internal adc outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see figure 68). each configuration corresponds to a current-sense gain (a cs ) of 3 v/v, 6 v/v, 12 v/v, 24 v/v, respectively (see table 5 and table 6). this variable is used for the valley current-limit setting, which sets up the appropriate current-sense gain for a given application and sets the compensation necessary to achieve loop stability (see the valley current-limit setting and compensation network sections). drvh drvl q1 sw q2 r res adp1872 cs gain programming 08297-066 figure 67. programming resistor location sw pgnd cs gain set cs amp adc drvl res 0.4v 08297-067 figure 68. res detect circuit for current-sense gain programming table 5. current-sense gain programming resistor a cs (v/v) 47 k 3 22 k 6 open 12 100 k 24 valley current-limit setting the architecture of the adp1872/ADP1873 is based on valley current-mode control. the current limit is determined by three components: the r on of the lower side mosfet, the error amplifier output voltage swing (comp), and the current-sense gain. the comp range is internally fixed at 1.4 v. the current-sense gain is programmable via an external resistor at the drvl pin (see the programming resistor (res) detect circuit section). the r on of the lower side mosfet can vary over temperature and usually has a positive t c (meaning that it increases with temperature); therefore, it is recommended to program the current-sense gain resistor based on the rated r on of the mosfet at 125c. because the adp1872/ADP1873 are based on valley current control, the relationship between i clim and i load is ? ? ? ? ? ? ??? 2 1 i load clim k ii where: i clim is the desired valley current limit. i load is the current load. k i is the ratio between the inductor ripple current and the desired average load current (see figure 10). establishing k i helps to determine the inductor value (see the inductor selection section), but in most cases, k i = 0.33. load current valley current limit ripple current = i load 3 0 8297-068 figure 69. valley current limit to average current relation when the desired valley current limit (i clim ) has been determined, the current-sense gain can be calculated by oncs clim ra i ? ? v4.1 where: a cs is the current-sense gain multiplier (see table 5 and table 6). r on is the channel impedance of the lower side mosfet. although the adp1872/ADP1873 have only four discrete current- sense gain settings for a given r on variable, table 6 and figure 70 outline several available options for the valley current setpoint based on various r on values.
adp1872/ADP1873 data sheet rev. b | page 20 of 40 table 6. valley current limit program 1 r on (m) valley current level 47 k 22 k open 100 k a cs = 3 v/v a cs = 6 v/v a cs = 12 v/v a cs = 24 v/v 1.5 38.9 2 29.2 2.5 23.3 3 39.0 19.5 3.5 33.4 16.7 4.5 26.0 13 5 23.4 11.7 5.5 21.25 10.6 10 23.3 11.7 5.83 15 31.0 15.5 7.75 3.87 18 26.0 13.0 6.5 3.25 1 refer to figure 70 for more infor mation and a graphical representation. 1234567891011121314151617181920 valley current limit (a) r on (m ? ) 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 res = 47k ? a cs = 3v/v res = 22k ? a cs = 6v/v res = no res a cs = 12v/v res = 100k ? a cs = 24v/v 08297-069 figure 70. valley current-limit value vs. r on of the lower side mosfet for each programming resistor (res) the valley current limit is programmed as outlined in table 6 and figure 70. the inductor chosen must be rated to handle the peak current, which is equal to the valley current from table 6 plus the peak-to-peak inductor ripple current (see the inductor selection section). in addition, the peak current value must be used to compute the worst-case power dissipation in the mosfets (see figure 71). inductor current valley current limit threshold (set for 25a) ? i = 33% of 30a comp output swing comp output 2.4v 1v 0a 35a 30a 32.25a 37a 49 a 39.5a ? i = 45% of 32.25a ? i = 65% of 37a maximum dc load current 08297-070 figure 71. valley current-limit threshold in relation to inductor ripple current hiccup mode during short circuit a current-limit violation occurs when the current across the source and drain of the lower side mosfet exceeds the current- limit setpoint. when 32 current-limit violations are detected, the controller enters idle mode and turns off the mosfets for 6 ms, allowing the converter to cool down. then, the controller re-establishes soft start and begins to cause the output to ramp up again (see figure 72). while the output ramps up, comp is monitored to determine if the violation is still present. if it is still present, the idle event occurs again, followed by the full-chip power-down sequence. this cycle continues until the violation no longer exists. if the violation disappears, the converter is allowed to switch normally, maintaining regulation. hs clim zero current repeated current limit violation detected a predetermined number of pulses is counted to allow the converter to cool down soft start is reinitialized t o monitor if the violation still exists 08297-071 figure 72. idle mode entry sequence due to current-limit violations
data sheet adp1872/ADP1873 rev. b | page 21 of 40 synchronous rectifier the adp1872/ADP1873 employ an internal lower side mosfet driver to drive the external upper side and lower side mosfets. the synchronous rectifier not only improves overall conduction efficiency but also ensures proper charging to the bootstrap capacitor located at the upper side driver input. this is beneficial during startup to provide sufficient drive signal to the external upper side mosfet and attain fast turn-on response, which is essential for minimizing switching losses. the integrated upper and lower side mosfet drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the mosfets or reduce efficiency as a result of excessive power loss. power saving mode (psm) version (ADP1873) the power saving mode version of the adp1872 is the ADP1873. the ADP1873 operates in the discontinuous conduction mode (dcm) and pulse skips at light load to midload currents. it outputs pulses as necessary to maintain output regulation. unlike the continuous conduction mode (ccm), dcm operation prevents negative current, thus allowing improved system efficiency at light loads. current in the reverse direction through this pathway, however, results in power dissipation and therefore a decrease in efficiency. hs hs and ls are off or in idle mode ls 0a i load as the inductor current approaches zero current, the state machine turns off the lower side mosfet. t on t off 08297-072 figure 73. discontinuous mode of operation (dcm) to minimize the chance of negative inductor current buildup, an on-board, zero-cross comparator turns off all upper side and lower side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper side and lower side mosfets are turned off. to ensure idle mode entry, a 10 mv offset, connected in series at the sw node, is implemented (see figure 74). 10mv zero-cross comparator q2 ls sw i q2 08297-073 figure 74. zero-cross comparator with 10 mv of offset as soon as the forward current through the lower side mosfet decreases to a level where 10 mv = i q2 r on(q2) the zero-cross comparator (or i rev comparator) emits a signal to turn off the lower side mosfet. from this point, the slope of the inductor current ramping down becomes steeper (see figure 75) as the body diode of the lower side mosfet begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted. hs and ls in idle mode 10mv = r on i load zero-cross comparator detects 10mv offset and turns off ls sw ls 0a i load t on another t on edge is triggered when v out falls below regulation 08297-074 figure 75. 10 mv offset to ensure pr evention of negative inductor current the system remains in idle mode until the output voltage drops below regulation. a pwm pulse is then produced, turning on the upper side mosfet to maintain system regulation. the ADP1873 does not have an internal clock; therefore, it switches purely as a hysteretic controller, as described in this section. timer operation the adp1872/ADP1873 employ a constant on-time architecture, which provides a variety of benefits, including improved load and line transient response when compared with a constant (fixed) frequency current-mode control loop of comparable loop design. the constant on-time timer, or t on timer, senses the high input voltage (vin) and the output voltage (v out ) using sw waveform information to produce an adjustable one-shot pwm pulse that varies the on-time of the upper side mosfet in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. it then generates an on-time (t on ) pulse that is inversely proportional to v in . vi n v kt out on ?? where k is a constant that is trimmed using an rc timer product for the 300 khz, 600 khz, and 1.0 mhz frequency options.
adp1872/ADP1873 data sheet rev. b | page 22 of 40 c r (trimmed) vdd t on vin i sw information 08297-075 figure 76. constant on-time timer the constant on-time (t on ) is not strictly constant because it varies with vin and v out . however, this variation occurs in such a way as to keep the switching frequency virtually independent of vin and v out . the t on timer uses a feedforward technique, applied to the constant on-time control loop, making it pseudo-fixed frequency to a first order. second-order effects, such as dc losses in the external power mosfets (see the efficiency consideration section), cause some variation in frequency vs. load current and line voltage. these effects are shown in figure 22 to figure 33. the variations in frequency are much reduced compared with the variations generated when the feedforward technique is not used. the feedforward technique establishes the following relationship: f sw = 1/ k where f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz). the t on timer senses vin and v out to minimize frequency variation with vin and v out as previously explained. this provides a pseudo-fixed frequency, see the pseudo-fixed frequency section for additional information. to allow headroom for vin/v out sensing, the following two equations must be adhered to. for typical applications where v dd is 5 v, these equations are not relevant; however, for lower v dd , care may be required. v dd vin /8 + 1.5 v dd v out /4 pseudo-fixed frequency the adp1872/ADP1873 employ a constant on-time control scheme. during steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. this is due to the one- shot t on timer that produces a high-side pwm pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. during load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation quicker than if the frequency were fixed or if it were to remain unchanged. after the transient event is complete, the frequency returns to a pseudo-fixed value to a first-order. to illustrate this feature more clearly, this section describes one such load transient eventa positive load stepin detail. during load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (drvl on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. when a positive load step occurs, the error amplifier (out of phase of the output, v out ) produces new voltage information at its output (comp). in addition, the current-sense amplifier senses new inductor current information during this positive load transient event. the error amplifiers output voltage reaction is compared to the new inductor current information that sets the start of the next switching cycle. because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifiers output (comp). the result is a convergence of these two signals (see figure 77), which allows an instantaneous increase in switching frequency during the positive load transient event. in summary, a positive load step causes v out to transient down, which causes comp to transient up and therefore shortens the off time. this resulting increase in frequency during a positive load transient helps to quickly bring v out back up in value and within the regulation window. similarly, a negative load step causes the off time to lengthen in response to v out rising. this effectively increases the inductor demagnetizing phase, helping to bring v out to within regulation. in this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. because the adp1872/ADP1873 has the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent . therefore, using a pseudo-fixed frequency, results in significantly better load transient performance than using a fixed frequency. valley trip points load current demand error amp output pwm output f sw > f sw cs amp output 08297-076 figure 77. load transient response operation
data sheet adp1872/ADP1873 rev. b | page 23 of 40 application s i nformation feedback resistor di vider the required resistor divider network can be determine for a given v out value because t he internal band gap reference (v ref ) is fixed at 0.6 v . s electing values for r t an d r b determine s the minimum output load current of the converter . therefore, f or a given value of r b , the r t value can be determined by v 6 . 0 v) 6 . 0 ( ? = out b t v r r inductor selection the inductor value is inversely proportional to th e inductor ripple current. the peak - to - peak ripple current is given by 3 load load i l i i k i = ? where k i is typically 0.33 . the equation for the inductor value is given by vin v f i v vin l out sw l out ? ? = ) ( where: v in is the high voltage input. v out is the desired output voltage . f sw is the c o ntroller switching frequency ( 300 khz , 600 kh z , and 1 .0 m h z) . when s electing the inductor, choose an inductor saturation rating that is above the peak current level and then calculate the inductor current ripple ( see the valley current - limit setting section and figure 78) . 52 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 6 8 10 12 14 16 18 20 22 24 26 28 30 peak inductor current (a) valley current limit (a) ?, ?, ?, 08297-077 figure 78 . peak current vs. vall ey current threshold for 33%, 40% , and 50 % of inductor ripple current table 7 . recommended inductors l (h) dcr (m) i sat (a) dimensions (mm) manufacturer model n o. 0.12 0.33 55 10.2 7 w rth elek tronic 744303012 0.22 0.33 30 10.2 7 w rth elektronic 744303022 0.47 0.8 50 14.2 12.8 w rth elektronic 744355147 0.72 1.65 35 10.5 10.2 w rth elektronic 744325072 0.9 1.6 28 1 3 12.8 w rth elektronic 744355090 1.2 1.8 25 10.5 10.2 w rth elektronic 744325120 1.0 3.3 20 10. 5 10.2 w rth elektronic 7443552100 1.4 3.2 24 14 12.8 w rth elektronic 744318180 2. 0 2.6 2 2 1 3 .2 12.8 w rth elektronic 7443551200 0.8 27.5 sumida cep125u - 0r8 output ripple voltag e ( v rr ) the output ripple voltage is the ac component of the dc output voltage during steady state. for a ripple error of 1.0%, the output capacitor value need ed to achieve this tolerance can be determined using the following equation . ( note that an accuracy of 1.0% is only possible during steady state conditions , not during load transients . ) v rr = (0.01) v out output capacitor sel ection the primary objective of the outp ut capacitor is to fa cilitate the reduction of the output voltage ripple ; however, the output capacitor also assist s in the output voltage recovery during load transient events. for a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. the speed at which the o utput voltage settles during this recovery period depend s on where the crossove r frequency (loop bandwidth) is set . this crossover frequency is determined by the output capacitor, the equivalent series resistance (esr) of the capacitor , and the compensation network. to c alculat e the small signal voltage ripple ( output ripple voltage ) at the steady state operating point , use the following equation: [ ] ? ? ? ? ? ? ? ? ? ? ? ? = ) ( 8 1 esr i v f i c l ripple sw l out where esr is the equivalent series resistance of the output capac itors. to calculate the output load step , use the following equation : )) ( ( 2 esr i v f i c load droop sw load out ? ? ? ? = where v droop is the amount that v out is allowed to deviate for a given positive load current step ( i load ).
adp1872/ADP1873 data sheet rev. b | page 24 of 40 ceramic capacitors are known to have low esr. however, the trade - off of using x5r technology is that up to 80% of its capaci - tance m ay be lost due to d erating because the voltage applied across the capacitor is increased (see figure 79) . although x7r series capacitors can also be used, the available selection is limited to only up to 22 f. 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 5 10 15 20 25 30 capacitance charge (%) dc voltage (v dc ) x7r (50v) x5r (25v) x5r (16v) 10f tdk 25v, x7r, 1210 c3225x7r1e106m 22f murata 25v, x7r, 1210 grm32er71e226ke15l 47f murata 16v, x5r, 1210 grm32er61c476ke15l 08297-078 figure 79 . capacitance vs. dc voltage characteristics f or ceramic capacitors electrolytic capacitors satisfy the bulk capacitance requirements for most high current application s . because the esr of electrolytic capacitors is much higher than that of ceramic cap a citors, when using electrolytic capacitors , several mlccs should be mounted in parallel to reduce the overall series resistance . compensation network due to its current - mode architecture, the adp1872/ADP1873 require type ii compensation. t o de termine the component values needed for compensation (resistance and capacitance value s), it is necessary to examine th e converters overall loop gain ( h ) at the unity gain frequency ( f sw /10) when h = 1 v/v . filt comp ref out cs m z z v v g g h = = v/v 1 ex amining each variable at high frequency enables the unity gain transfer function to be s implified to provide expression s for the r comp and c comp component values. output filter impedance (z filt ) examining the filters transfer function at high frequencies simplifies to out filter sc z 1 = at the cross over frequency (s = 2 f cross ). error amplifier output impedance (z comp ) assuming c c 2 is significantly smaller than c comp , c c 2 can be omitted from the output impedance equation of the error amp lifier . the transfer function simplif ies to cross zero cross comp comp f f f r z ) ( + = and sw cross f f = 12 1 where f zero , the zero frequency , is set to be 1/4 th of the c ross over frequency for the adp1872. error amplifier gain (g m ) the error amplifier gain (transconductance) is g m = 500 a/v current - sense loop gain ( g cs ) the curr ent - sense loop gain is on cs cs r a g = 1 (a/v) w here : a cs (v/v) is programmable for 3 v/v , 6 v/v , 12 v / v, and 24 v/v (see the programming resistor (res) detect circuit and valley cur rent - limit setting sections ) . r on is the channel impedance of the low er side mosfet . crosso ver frequency the crossover frequency is the f requency at which the overall loop (system) gain is 0 db (h = 1 v/v). it is recommended for current - mode converters , such as the adp1872 , that the user set the cross over frequency between 1/10 th and 1/15 th of the switching frequency. sw cross f f 12 1 = the relationship between c comp and f zero (zero frequency ) is comp comp zero c r f = 2 1 the zero frequency is set to 1/4 th of the cross over frequency. combining all of the above parameters result s in ref out cs m out cross zero cross cross comp v v g g c f f f f r + = 2 zero comp comp f r c = 2 1
data sheet adp1872/ADP1873 rev. b | page 25 of 40 efficiency consideration one of the important criteria to consider in constructing a dc-to-dc converter is efficiency. by definition, efficiency is the ratio of the output power to the input power. for high power applications at load currents up to 20 a, the following are important mosfet parameters that aid in the selection process: ? v gs (th) : the mosfet support voltage applied between the gate and the source. ? r ds (on) : the mosfet on resistance during channel conduction. ? q g : the total gate charge ? c n1 : the input capacitance of the upper side switch ? c n2 : the input capacitance of the lower side switch the following are the losses experienced through the external component during normal switching operation: ? channel conduction loss (both the mosfets) ? mosfet driver loss ? mosfet switching loss ? body diode conduction loss (lower side mosfet) ? inductor loss (copper and core loss) channel conduction loss during normal operation, the bulk of the loss in efficiency is due to the power dissipated through mosfet channel conduction. power loss through the upper side mosfet is directly proportional to the duty cycle (d) for each switching period, and the power loss through the lower side mosfet is directly proportional to 1 ? d for each switching period. the selection of mosfets is governed by the amount of maximum dc load current that the converter is expected to deliver. in particular, the selection of the lower side mosfet is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. therefore, the lower side mosfet is in the on state for most of the switching period. p n1, n2 (cl) = [ d r n1 (on) + (1 ? d ) r n2 (on) ] 2 load i mosfet driver loss other dissipative elements are the mosfet drivers. the contributing factors are the dc current flowing through the driver during operation and the q gate parameter of the external mosfets. ? ? ? ? ?? ?? bias dd lowerfet sw dd bias dr upperfet sw dr lossdr ivcfv ivcfv p ? ? ?? ?? )( where: c upperfet is the input gate capacitance of the upper-side mosfet. c lowerfet is the input gate capacitance of the lower-side mosfet. v dr is the driver bias voltage (that is, the low input voltage (v dd ) minus the rectifier drop (see figure 80)). i bias is the dc current flowing into the upper- and lower-side drivers. v dd is the bias voltage. 800 720 640 560 480 400 320 240 160 80 300 1000 900 800 700 600 500 400 rectifier drop (mv) frequency (khz) +125c +25c ?40c v dd = 2.7v v dd = 3.6v v dd = 5.5v 08297-079 figure 80. internal rectifier voltage drop vs. switching frequency mosfet switching loss the sw node transitions due to the switching activities of the upper side and lower side mosfets. this causes removal and replenishing of charge to and from the gate oxide layer of the mosfet, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. the current that enters and exits these charge paths presents additional loss during these transition times. this can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions. t sw-trans = r gate c total where: r gate is the gate input resistance of the mosfet. c total is the c gd + c gs of the external mosfet used. the ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: 2 - )( ??? ? vini t t p load sw transsw losssw or p sw (loss) = f sw r gate c total i load vin 2
adp1872/ADP1873 data sheet rev. b | page 26 of 40 body diode conduction loss the adp1872/ADP1873 employ anticross conduction circuitry that prevents the upper side and lower side mosfets from conducting current simultaneously. this overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. however, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the mosfets change states and continuing well into idle mode. the amount of loss through the body diode of the lower side mosfet during the antioverlap state is given by 2 )( )( ??? ? f load sw loss body loss body vi t t p where: t body (loss) is the body conduction time (refer to figure 81 for dead time periods). t sw is the period per switching cycle. v f is the forward drop of the body diode during conduction. (refer to the selected external mosfet data sheet for more information about the v f parameter.) 80 72 64 56 48 40 32 24 16 8 2.7 5.5 4.8 4.1 3.4 body diode conduction time (ns) v dd (v) +125c +25c ?40c 1mhz 300khz 08297-080 figure 81. body diode conduction time vs. low voltage input (v dd ) inductor loss during normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (dcr). typically, larger sized inductors have smaller dcr values. the inductor core loss is a result of the eddy currents generated within the core material. these eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. the amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. it is recommended to use shielded ferrite core material type inductors with the adp1872/ADP1873 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (emi). p dcr (loss) = dcr 2 load i + core loss input capacitor selection the goal in selecting an input capacitor is to reduce or to minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. the problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (esr) and large equivalent series inductance (esl). aluminum electrolytic capacitors have such high esr that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. if bulk capacitors are to be used, it is recommended to use multi- layered ceramic capacitors (mlcc) in parallel due to their low esr values. this dramatically reduces the input voltage ripple amplitude as long as the mlccs are mounted directly across the drain of the upper side mosfet and the source terminal of the lower side mosfet (see the layout considerations section). improper placement and mounting of these mlccs may cancel their effectiveness due to stray inductance and an increase in trace impedance. ?? out out out max load rmscin v vvinv ii ?? ? ? , , the maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 ? d while the upper side mosfet is in the off state. the input capacitor rms current reaches its maximum at time d. when calculating the maximum input voltage ripple, account for the esr of the input capacitor as follows: v max, ripple = v ripp + ( i load, max esr ) where: v ripp is usually 1% of the minimum voltage input. i load, max is the maximum load current. esr is the equivalent series resistance rating of the input capacitor used. inserting v max, ripple into the charge balance equation to calculate the minimum input capacitor requirement gives sw ripple max max load min in, f dd v i c )1( , , ? ? ? or ripple max sw max load min in, vf i c , , 4 ? where d = 50%.
data sheet adp1872/ADP1873 rev. b | page 27 of 40 thermal consideratio ns the adp1872/ADP1873 are used for dc - to - dc , step down, high current applications that have an on - board controller and on - board m osfet drivers. because applications may requir e up to 20 a of load current delivery and be subjected to high ambient temperature surroundings , the selection of external upper side and lower side mosfet s must be associated with careful thermal consid eration to not exceed the maximum allowable junction temperature of 125c . to avoid permanent or irreparable damage i f the junction temperature reaches or exceeds 155c, the part enter s thermal shutdown , turning off both external mosfets , and does not re - enable until the junction temperature cools to 140c ( see the thermal shutdown section ). the maximum junction temperature allowed for the adp1872/ adp 1873 ic s is 125c. this means that the sum of the ambient temp era ture (t a ) and the rise in package temperature (t r ), which is c aused by the thermal impedance of the package and the internal power dissipation , should not exceed 125c , as dictated by t j = t r t a w here : t j is the maximum junction temperature. t r is t he rise in package temperature due to the power dissipated from within. t a is the ambient temperature. the rise in package temperature is directly proportional to its thermal impedance characteristics. the following equation represents this proportionality relationship: t r = ja p dr (loss) w here : ja i s the thermal resistance of the package from the junction to the outside surface of the die , where it meets the surrounding air. p dr (loss) is the overall power dissipated by the ic. t he bulk of the power dissipated is due to t he gate capa citance of the external mosfet s. t he power loss equation of the mosfet drivers ( see the mosfet driver loss section in the efficiency consideration section ) is p dr (loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ v dd ( f sw c lowerfet v dd + i bias )] where: c upperfet is the input gate capacitance of the upper side mosfet . c lowerfet is the input gate capacitance of the lower side mosfet . i bias is the dc current (2 ma) flow ing into the upper side and lower side drivers. v dr is the driver bias voltage ( that is, the low input voltage (v dd ) minus the rectifier drop (see figure 80) ) . v dd is the bias voltage for example, if the external mosfet characteristics are ja (10 - lead msop) = 171.2c/w, f sw = 300 khz, i bias = 2 ma, c upperfet = 3.3 nf, c lowerfet = 3.3 nf, v dr = 5.12 v, and v dd = 5 . 5 v, then the power loss is p dr (loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ v dd ( f sw c lowerfet v dd + i bias )] = [ 5.12 (300 10 3 3.3 10 ?9 5.12 + 0.002)] + [5.5 (300 10 3 3.3 10 ?9 5.5 + 0.002)] = 77.13 mw the rise in package temperature is t r = ja p dr (loss) = 171.2c 77.13 mw = 13.2c assuming a maximum ambient temperature environment of 85c, the junction t emperature is t j = t r t a = 13.2c + 85c = 98.2c which is below the maximum junction temperature of 125c. design example the adp1872/ADP1873 are easy to use, requiring only a few design criteria. for example, the example outlined in this section uses o nly four d esign criteria : v out = 1.8 v , i load = 15 a (pulsing) , vin = 12 v (typical) , and f sw = 300 kh z . input capacitor the maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 v 0.01 = 120 mv). v ripp = 120 mv v max, ripple = v r ipp ? ( i load, max esr ) = 120 mv ? (15 a 0.001) = 45 mv mv 105 10 300 4 a 15 4 3 , , = = ripple max sw max load min in, v f i c = 120 f choose five 22 f ceramic capacitors. the overall esr of five 22 f ceramic capacitors is less than 1 m. i rms = i load / 2 = 7.5 a p cin = ( i rms ) 2 esr = (7.5a) 2 1 m = 56.25 mw inductor determining inductor ripple current amplitude: 3 load l i i ? = 5 a so calculating for the inductor value v 2 . 13 v 8 . 1 10 300 v 5 ) v 8 . 1 v 2 . 13 ( ) ( 3 , ? = ? ? = max in, out sw l out max in v v f i v v l = 1.03 h
adp1872/ADP1873 data sheet rev. b | page 28 of 40 the inductor peak current is approximately 15 a + (5 a 0.5) = 17.5 a therefore, an appropriate inductor selection is 1.0 h with dcr = 3.3 m (7443552100) from table 7 with peak current handling of 20 a. 2 ) ( load loss dcr i dcr p = = 0.003 (15 a) 2 = 675 mw current limit programming the v alley curr ent is approximately 15 a ? (5 a 0.5) = 12.5 a assuming a low er side mosfet r on of 4. 5 m , choosing 13 a as the valley current limit from table 6 and figure 70 indicates that a programming resistor (res) of 100 k corresponds to a n a cs of 24 v / v. choose a programmable resistor of r res = 100 k? for a current - sense gain of 24 v / v. output capacitor assume a load step of 15 a occurs at the output and no more than 5% is allowe d for the output to deviate from the steady state operating point. the adp1872s advantage is, because the frequency is pseudo - fixed, the converter is able to respond quickly because of the immediate, though temporary , increase in switching frequency. v d roop = 0.05 1.8 v = 90 mv assuming the overall esr of the output capacitor ranges from 5 m to 10 m, ) mv 90 ( 10 300 15 2 ) ( 2 3 = ? ? = a v f i c droop sw load out = 1.11 mf therefore, an appropriate i nductor selection is five 270 f polymer capacitors with a combined esr of 3.5 m. assuming an over shoot of 45 mv , d etermine if the output capacitor that was calculated previously is adequate: ( ) ( ) 2 2 2 6 2 2 2 ) 8 . 1 ( ) mv 45 8 . 1 ( ) a 15 ( 10 1 ) ( ) ( ? ? = ? ? ? = ? out ovsht out load out v v v i l c = 1.4 mf choose five 270 f polymer capacitors. the rms current through the output capacitor is a 49 . 1 v 2 . 13 v 8 . 1 10 300 f 1 ) v 8 . 1 v 2 . 13 ( 3 1 2 1 ) ( 3 1 2 1 3 , , = ? = ? = max in out sw out max in rms v v f l v v i the powe r loss dissipated thro ugh the esr of the output capacitor is p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw feedback resistor network setup it is recommended to use r b = 15 k . calculate r t as k 30 v 6 . 0 v) 6 . 0 v 8 . 1 ( k 15 = ? = t r compensation network t o calculate r comp , c comp , and c par , the transconductance parameter and the current - sense gain variable are requi red. the t ransconductance parameter ( g m ) is 500 a/v , and the c urrent - sense loop gain is a/v 33 . 8 005 . 0 24 1 1 = = = on cs cs r a g where a cs and r on are taken from setting up the current limit ( see the programming resistor (res) dete ct circuit and valley current - limit setting sections ). the crossover f requency is 1/12 th of the switching frequency: 300 k h z/12 = 25 k h z the zero frequency is 1/4 th of the cross over frequency: 25 k h z/4 = 6.25 k h z 6 . 0 8 . 1 3 . 8 10 500 10 11 . 1 10 25 141 . 3 2 10 25 . 6 10 25 10 25 2 6 3 3 3 3 3 + = + = ? ? ref out cs m out cross zero cross cross comp v v g g c f f f f r = 100 k zero comp comp f r c = 2 1 = 3 3 10 25 . 6 10 100 14 . 3 2 1 = 250 pf
data sheet adp1872/ADP1873 rev. b | page 29 of 40 loss calculations d uty cycle = 1.8/12 v = 0.15 r on (n2) = 5 .4 m t body(loss) = 20 ns ( body conduction time) v f = 0.84 v ( mosfet forward voltage ) c in = 3 .3 n f ( mosfet gate input capacitance ) q n1, n2 = 17 nc ( total mosfet gate charge ) r gate = 1.5 ( mosfet gate input resistance ) ( ) [ ] 2 1 load n2(on) n1(on) n2(cl) n1, i r d r d p ? + = = (0.15 0.0054 + 0.85 0.0054) (15 a) 2 = 1.21 5 w 2 ) ( ) ( = f load sw loss body loss body v i t t p = 20 ns 300 10 3 15 a 0.8 4 2 = 151.2 mw p sw (loss) = f sw r gate c total i load vin 2 = 300 10 3 1.5 ? 3.3 10 ?9 15 a 12 2 = 534.6 m w ( ) [ ] ( ) [ ] bias dd lowerfet sw dd bias dr upperfet sw dr loss dr i v c f v i v c f v p + + + = ) ( = (5.12 (300 10 3 3.3 10 ?9 5.12 + 0.002)) + (5.5 (300 10 3 3.3 10 ?9 5.5 + 0.002)) = 77.1 3 mw p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw 2 ) ( load loss dcr i dcr p = = 0.003 (15 a) 2 = 675 mw p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw p loss = p n1, n2 + p body (loss) + p sw + p dcr + p dr + p cout + p cin = 1.215 w + 151.2 mw + 534.6 m w + 77.13 m w + 3.15 mw + 675 mw + 56.25 mw = 2.62 w
adp1872/ADP1873 data sheet rev. b | page 30 of 40 external component r ecommendations the c onfigurations listed in table 8 are with f cross = 1/12 f sw , f zero = ? f cross , r res = 100 k , r bot = 15 k , r on = 5.4 m ? ( bsc042n03 ms g) , v dd = 5 v, and a maximum load current of 14 a. the ADP1873 models listed in table 8 are the psm versions of the device. table 8 . external component values marking code sap model adp1872 ADP1873 v out (v) vin (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) adp1872armz - 0.3- r7/ ADP1873armz - 0.3- r7 ldt ldf 0.8 13 5 22 2 5 560 3 0.72 47 740 74 5.0 ldt ldf 1.2 13 5 22 2 4 560 3 1.0 47 740 74 15.0 ldt ldf 1.8 13 4 22 2 4 270 4 1.0 47 571 57 30.0 ldt ldf 2.5 13 4 22 2 3 270 4 1.53 47 571 57 47.5 ldt ldf 3.3 13 5 22 2 2 330 5 2.0 47 571 57 67.5 ldt ldf 5 13 4 22 2 330 5 3.27 34 800 80 110.0 ldt ldf 7 13 4 22 2 22 2 + ( 4 47 6 ) 3.44 34 800 80 160.0 ldt ldf 1.2 16.5 4 22 2 4 56 0 3 1.0 47 740 74 15.0 ldt ldf 1.8 16.5 3 22 2 4 270 4 1.0 47 592 59 30.0 ldt ldf 2.5 16.5 3 22 2 4 270 4 1.67 47 592 59 47.5 ldt ldf 3.3 16.5 3 22 2 2 330 5 2.00 47 592 59 67.5 ldt ldf 5 16.5 3 22 2 2 150 7 3.84 34 829 83 110.0 ldt ldf 7 16.5 3 22 2 22 2 + 4 47 6 4.44 34 829 83 160.0 adp1872armz - 0.6- r7/ ADP1873armz - 0.6- r7 ldu ldk 0.8 5.5 5 22 2 4 560 3 0.22 47 339 34 5.0 ldu ldk 1.2 5.5 5 22 2 4 270 4 0.47 47 326 33 15.0 ldu ldk 1.8 5.5 5 22 2 3 270 4 0.47 47 271 27 30.0 ldu ldk 2.5 5.5 5 22 2 3 180 8 0.47 47 271 27 47.5 ldu ldk 1.2 13 3 22 2 5 270 4 0.47 47 407 41 15.0 ldu ldk 1.8 13 5 10 9 3 330 5 0.47 47 307 31 30.0 ldu ldk 2.5 13 5 10 9 3 270 4 0.90 47 307 31 47.5 ldu ldk 3.3 13 5 10 9 2 270 4 1.00 47 307 31 67.5 ldu ldk 5 13 5 10 9 150 7 1.76 34 430 43 110.0 ldu ldk 1.2 16.5 3 10 9 4 270 4 0.47 47 362 36 15.0 ldu ldk 1.8 16.5 4 10 9 2 330 5 0.72 47 326 33 30.0 ldu ldk 2.5 16.5 4 10 9 3 270 4 0.90 47 326 33 47.5 ldu ldk 3.3 16.5 4 10 9 330 5 1.0 47 296 30 67.5 ldu ldk 5 16.5 4 10 9 4 47 6 2.0 34 415 41 110.0 ldu ldk 7 16.5 4 10 9 3 47 6 2.0 34 380 38 160.0 adp1872ar mz - 1.0- r7/ ADP1873armz - 1.0- r7 ldv ldl 0.8 5.5 5 22 2 4 270 4 0.22 47 223 22 5.0 ldv ldl 1.2 5.5 5 22 2 2 330 5 0.22 47 223 22 15.0 ldv ldl 1.8 5.5 3 22 2 3 180 8 0.22 47 163 16 30.0 ldv ldl 2.5 5.5 3 22 2 270 4 0.22 47 163 16 47.5 ldv ldl 1.2 13 3 10 9 3 330 5 0 .22 47 233 23 15.0 ldv ldl 1.8 13 4 10 9 3 270 4 0.47 47 210 21 30.0 ldv ldl 2.5 13 4 10 9 270 4 0.47 47 210 21 47.5 ldv ldl 3.3 13 5 10 9 270 4 0.72 47 210 21 67.5 ldv ldl 5 13 4 10 9 3 47 6 1.0 34 268 27 110.0 ldv ldl 1.2 16.5 3 10 9 4 270 4 0.47 47 326 33 15. 0 ldv ldl 1.8 16.5 3 10 9 3 270 4 0.47 47 261 26 30.0 ldv ldl 2.5 16.5 4 10 9 3 180 8 0.72 47 233 23 47.5 ldv ldl 3.3 16.5 4 10 9 270 4 0.72 47 217 22 67.5
data sheet adp1872/ADP1873 rev. b | page 31 of 40 marking code sap model adp1872 ADP1873 v out (v) vin (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) ldv ldl 5 16.5 3 10 9 3 47 6 1.0 34 268 27 110.0 ldv ldl 7 16.5 3 10 9 22 2 + 47 6 1.0 34 228 23 160.0 1 see the inductor selection section (see table 9 ) . 2 22 f murata 25 v , x7r , 1210 g rm32er71e226ke15l (3.2 mm 2.5 mm 2.5 mm) . 3 560 f panasonic ( sp - series ) 2 v, 7 m , 3.7 a eefue0d561lr ( 4.3 mm 7.3 mm 4.2 mm ). 4 270 f panasonic (sp - series) 4 v, 7 m , 3.7 a eefue0g271lr ( 4.3 mm 7.3 mm 4.2 mm ). 5 330 f panasonic (sp - series) 4 v, 12 m , 3.3 a eefue0g331r ( 4.3 mm 7.3 mm 4.2 mm ). 6 47 f murata 16 v , x5r , 1210 grm32er61c476ke15l (3.2 mm 2.5 mm 2.5 mm) . 7 150 f panasonic (sp - series) 6.3 v, 10 m , 3.5 a eefue0j151xr ( 4.3 mm 7.3 mm 4.2 mm ). 8 180 f panasonic (sp - series ) 4 v, 10 m , 3.5 a eefue0g181xr ( 4.3 mm 7.3 mm 4.2 mm ). 9 10 f tdk 25 v , x7r , 1210 c3225x7r1e106m . table 9 . recommended inductors l (h) dcr (m) i sat (a) dimension (mm) manufacturer model number 0.12 0.33 55 10.2 7 wrth elektronik 744303012 0.22 0.33 30 10.2 7 w rth elektronik 744303022 0.47 0.8 50 14.2 12.8 wrth elektronik 744355147 0.72 1.65 35 10.5 10.2 wrth elektronik 744325072 0.9 1.6 28 13 12.8 wrth elektronic 744355090 1.2 1.8 25 10.5 10.2 wrth elektronic 744325120 1.0 3.3 20 10.5 10.2 w rth elektronic 7443552100 1.4 3.2 24 14 12.8 wrth elektronic 744318180 2.0 2.6 22 13.2 12.8 wrth elektronic 7443551200 0.8 27.5 sumida cep125u - 0r8 table 10. recommended mosfet s v gs = 4.5 v r on (m) i d (a) v ds (v) c in (nf) q total (nc) package manufacturer model number upper - side mosfet (q1/q2) 5.4 47 30 3.2 20 pg - tdson8 infineon bsc042n03 ms g 10.2 53 30 1.6 10 pg - tdson8 infineon bsc080n03 ms g 6.0 19 30 35 so -8 vishay si4842dy 9 14 30 2.4 25 so -8 international rectifier irf7811 low er- side mosfet (q3/q4) 5.4 47 30 3.2 20 pg - tdson8 infineon bsc042n03 ms g 10.2 82 30 1.6 10 pg - tdson8 infineon bsc080n03 ms g 6.0 19 30 35 so -8 vishay si4842dy
adp1872/ADP1873 data sheet rev. b | page 32 of 40 layout consideration s t he performance of a dc - to - dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (pcb) . optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulatio n specifications , and reduce pwm jitter and electromagnetic interference. figure 82 shows the schematic of a typical adp1872 /ADP1873 used for a high power application. blue traces denote high current pathways. vin , pgnd , and v out tra ces should be wide and possibly replicated, descending down into the multiple layers. vias should populate , mainly around the positive and negative terminal s of the input and output capacitors , alongside the source of q1/q2, the drain o f q3/q4, and the inductor . mur at a: (high vo lt age input ca p aci t ors) 22 f , 25 v , x7r, 1210 grm32er71e226ke15 l p anasonic: (output ca p aci t ors) 270f (sp-series) 4 v , 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower-side) bsc080n03ms g (upper-side) wurth inductors: 1h, 3.3m?, 20a 7443552100 r5 100k? q3 q4 q1 q2 high voltage input vin = 12v c12 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c23 270f + c22 270f + c21 270f + c20 270f + 1.0h r6 2? c13 1.5nf r1 30k? r2 15k? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vdd 6 drvl adp1872/ ADP1873 c c 571pf c f 57pf r c 47k? c1 1f c2 0.1f low voltage input v dd = 5.0v jp1 08297-081 figure 82 . adp1872/ADP1873 high current evaluation board schematic (blue traces indicate high current paths )
data sheet adp1872/ADP1873 rev. b | page 33 of 40 08297-082 output capacitors are mounted on the rightmost area of the evb, wrapping back around to the main power ground plane, where it meets with the negative terminals of the input capacitors input capacitors are mounted close to drain of q1/q2 and source of q3/q4. bypass power capacitor (c1) for vreg bias decoupling and high frequency capacitor (c2) as close as possible to the ic. sensitive analog components located far from the noisy power section. separate analog ground plane for the analog components (that is, compensation and feedback resistors). figure 83 . overall layout of the adp187 2 high current evalua tion board sw
adp1872/ADP1873 data sheet rev. b | page 34 of 40 08297-083 figure 84 . layer 2 of evaluation board
data sheet adp1872/ADP1873 rev. b | page 35 of 40 top resistor feedback tap vout sense tap line extending back to the top resistor in the feedback divider network (see figure 82). this overlaps with pgnd sense tap line extending back to the analog plane (see figure 86, layer 4 for pgnd tap). 08297-084 figure 85 . layer 3 of evaluation board
adp1872/ADP1873 data sheet rev. b | page 36 of 40 08297-085 bottom resistor tap to the analog ground plane pgnd sense tap from negative terminals of output bulk capacitors. this track placement should be directly below the vout sense line from figure 84. figure 86 . layer 4 ( bottom layer ) of evaluation board
data sheet adp1872/ADP1873 rev. b | page 37 of 40 ic section (left side of e valuation board ) a dedicated plane for the analog ground plane ( gnd ) sh ould be separate from the main power ground plane (pgnd). with the shortest path possibl e, connect the analog ground plane to the gnd pin ( pin 4). this plane should only be on the top l ayer of the evaluat ion board. to avoid cross talk interference , there should not be any other voltage or current pathway directly below this plane on layer 2, layer 3 , or layer 4. connect the negative terminals of all sensitive analog components to the anal og ground plane. examples of s uch sensitive analog com - ponents include the resistor dividers bottom resistor, the high frequency bypass capacitor for biasing (0.1 f) , and the compensation network . mount a 1 f bypass capacitor directly acr oss the v dd pi n ( pin 5) and the pgnd pin ( pin 7 ). in addition , a 0.1 f should be tied across the v dd pin ( pin 5) and the gnd pin ( pin 4 ) . power section as shown i n figure 83, an appropriate configuration to localize large curr ent transfer from the high voltage input (vin) to the output (v out ) a nd then back to the power ground is to put the v in plane on the left, the output plane on the right , and the main power ground plane in between the two. c urrent transfers from the input c apa citors to the output capacitors, through q1 /q2 , during the on state ( see figure 87) . the direction of this current ( yellow arrow ) is maintained as q1 /q2 turns off and q3/q4 turns on. when q 3/q4 turns on, the cur rent direction continues to be maintained ( red arrow ) as it circles from the bulk capacitors power ground terminal to the output capacitors , through the q3/q4. arr anging the power planes in this manner minimizes the area in which changes in flux occur if the current through q1 /q 2 stops abruptly . s udden change s in flux , usually at source terminals of q1/q2 and drain terminal s of q3/q4, cause large dv/dt s at the sw node . the sw node is near the top of the evaluation board. the sw node should use the least a mount of area p ossible and be away from any sensitive analog circuitry and components because this is where most sudden change s in flux densi ty occur . when possible, replicate this pad onto layer 2 and layer 3 for thermal relief and eliminate any other vol tage and current pathways directly beneath the sw node plane. populate the sw node plane with vias , mainly around the exposed pad of the inductor terminal and around the perimeter of the source of q1/q2 and the drain of q3/q4. the output voltage pow er plan e (vout) is at the right - most end of the evaluation board. this plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminal s of the output bulk capacitors . ensure that the negative te rminals of the output capacitors are placed close to the main power ground (pgnd) , as previously mentioned. all of the se points form a tight circle (component geometry permitting) that minimize s the area of flux change as the event switch es between d and 1 ? d . vout sw vin pgnd 08297-086 figure 87 . primary current pathways during the on state of the upper - side mosfet ( left arrow ) and the on state of the lower - side mosfet ( right arrow) differential sensing because the adp187 2 /adp187 3 operate in valley curre nt - mode control, a differential voltage reading is taken across the drain and source of the lower - side mosfet. the drain of the lower - side mosfet should be connected as close as possible to the sw pin (pin 9) of the ic. likewise, the source should be conne cted as close as possible to the pgnd pin (pin 7) of the ic. when possible, both of these track lines should be narrow and away from any other active device or voltage/current paths. 08297-087 layer 1: sense line for sw (drain of lower mosfet) layer 1: sense line for pgnd (source of lower mosfet) sw pgnd figure 88 . drain/source tracking tapping of t he lower - side mosfet for cs amp differential sensing (yellow sense line on layer 2) differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see figure 85 and figure 86 ). connect the positive terminal of the output capacitor to the top resistor (r t ). connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current paths.
adp1872/ADP1873 data sheet rev. b | page 38 of 40 typical application circuits dual - input , 300 k h z high current application circuit mur at a: (high vo lt age input ca p aci t ors) 22 f , 25 v , x7r, 1210 grm32er71e226ke15 l p anasonic: (output ca p aci t ors) 270f (sp-series) 4 v , 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower-side) bsc080n03ms g (upper-side) wurth inductors: 1h, 3.3m?, 20a 7443552100 r5 100k? q3 q4 q1 q2 high voltage input vin = 12v c12 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c23 270f + c22 270f + c21 270f + c20 270f + 1.0h r6 2? c13 1.5nf r1 30k? r2 15k? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vdd 6 drvl adp1872/ ADP1873 c c 571pf c f 57pf r c 47k? c1 1f c2 0.1f low voltage input v dd = 5.0v jp1 08297-088 figure 89 . ap plication circuit fo r 12 v input , 1.8 v output, 15 a, 300 kh z (q2/q4 no connect) . single - input , 600 k h z application circuit mur at a: (high vo lt age input ca p aci t ors) 22 f , 25 v , x7r, 1210 grm32er71e226ke15 l p anasonic: (output ca p aci t ors) 180f (sp-series) 4 v , 10m? eefue0g181xr infineon mosfets: bsc042n03ms g (lower-side) bsc080n03ms g (upper-side) wurth inductors: 0.47h, 0.8m?, 50a 744355147 r5 100k? q3 q4 q1 q2 high voltage input vin = 5.5v c12 100nf v out = 2.5v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c22 180f + c21 180f + c20 180f + 0.47h r6 2? c13 1.5nf r1 47.5k? r2 15k? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vdd 6 drvl adp1872/ ADP1873 c c 271pf c f 27pf r c 47k? c1 1f c2 0.1f jp1 08297-089 figure 90 . application circuit for 5.5 v input , 2.5 v output, 15 a, 600 kh z (q2/q4 no connect)
data sheet adp1872/ADP1873 rev. b | page 39 of 40 dual - input , 300 k h z high current application circuit mur at a: (high vo lt age input ca p aci t ors) 22 f , 25 v , x7r, 1210 grm32er71e226ke15 l p anasonic: (output ca p aci t ors) 270f (sp-series) 4 v , 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower-side) bsc080n03ms g (upper-side) wurth inductors: 0.72h, 1.65m?, 35a 744325072 q3 q4 q1 q2 high voltage input vin = 13v low voltage input v dd = 5v c12 100nf v out = 1.8v, 20a c3 22f c4 22f c5 22f c6 22f c7 22f c23 270f + c22 270f + c21 270f + c20 270f + 0.8h r6 2? c13 1.5nf r1 30k? r2 15k? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vdd 6 drvl adp1872/ ADP1873 c c 800pf c f 80pf r c 33.5k? c1 1f c2 0.1f jp1 08297-090 figure 91 . application circuit for 13 v input , 1.8 v output, 20 a, 300 kh z (q2/q4 no connect)
adp1872/ADP1873 data sheet rev. b | page 40 of 40 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 92. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adp1872armz-0.3-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldt adp1872armz-0.6-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldu adp1872armz-1.0-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldv adp1872-0.3-evalz forced pwm, 300 khz evaluation board adp1872-0.6-evalz forced pwm, 600 khz evaluation board adp1872-1.0-evalz forced pwm, 1 mhz evaluation board ADP1873armz-0.3-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldf ADP1873armz-0.6-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldk ADP1873armz-1.0-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldl ADP1873-0.3-evalz power saving mode, 300 khz evaluation board ADP1873-0.6-evalz power saving mode, 600 khz evaluation board ADP1873-1.0-evalz power saving mode, 1 mhz evaluation board 1 z = rohs compliant part. ?2009C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08297-0-7/12(b)

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